Paolo A. Gargini

Developer of the building blocks of HMOS III and CHMOS III technologies used in the 1980s for the 80286 and the 80386 processors, Gargini has served as Director of Technology Strategy and Fellow of Technology & Manufacturing Group at Intel Corporation in Santa Clara, California. He has also been responsible for world-wide research activities conducted outside Intel for the Technology and Manufacturing Group by consortia, institutes, and universities. Since joining Intel in 1978, Gargini conducted studies on Process Reliability and was responsible for developing the building blocks of HMOS III and CHMOS III technologies used in the 1980s for the 80286 and the 80386 processors.

He was born in Florence, Italy and received a Doctorate in Electrical Engineering in 1970 and a Doctorate in Physics in 1975 from the Universita di Bologna, Italy, both with full honor and marks. He conducted research at LAMEL in Bologna, Stanford Electronics Laboratory, and Fairchild Camera and Instrument Research and Development in Palo Alto, California from 1970 to 1977. In 1985, Gargini headed the first submicron process development team at Intel.

He has served as Chairman of the Executive Steering Council (ESC) of I300I and, subsequently, of International Sematech from 1996 to 2000. From 1998, he has served as Chairman of the International Technology Roadmap for Semiconductors (ITRS). Gargini has also served as Member of the Scientific Advisory Board at Interuniversity MicroElectronics Center and as a member of the Sematech Board.

He has been a member of various technical committees and technical advisory boards for organizations such as the Silicon Research Corporation (SRC), the Technology Strategic Council (TSC) of the SIA in the US, IMEC in Europe, and ASET and MIRAI in Japan. He also headed the International EUV Initiative (IEUVI), formed in 2001, that fostered cooperation and coordination among the largest EUV consortia in the world. Gargini has additionally served as facilitator of the International Consortia Cooperation Initiative (ICCI).

In September 2003, he was included by EE Times in a very select group of Influencers of the semiconductor industry with the following motivation: "EE Times has chosen 13 people who are influencing the course of semiconductor development technology and taking it into realms that exceed the bounds set by the inventors of the transistor more than 50 years ago. With more than 25 years in the industry, Dr. Gargini is helping to navigate tough process and manufacturing waters."

He initiated and became the first Chairman of the Governing Council of the Nano Electronics Research Initiative (NERC), funded in June 2005 by SIA. This initiative was aimed at supporting and focusing research in universities towards the subsequent commercialization of Nanoelectronics. NERC actively cooperated in this effort with USG organizations such as NNI, NSF, DARPA, and NIST.